The invention relates to a semiconductor memory comprising a charge-coupled device of the SPS type having a series input register, a parallel section and a series output register, the number of data that can be stored per line in the parallel section being the n-multiple (where n=integer larger than or equal to 2) of the number of data that can be stored in the series input register and the series output register, while at the transition between the parallel section and the series output register an electrode configuration is present (designated as de-interlacing electrodes), by means of which a line of data in the parallel section can be split up into n sublines which can be transported successively in the series output register, the parallel section being provided with clock voltage means with the aid of which the data are transported at an adjustable speed through the parallel section.
Series-parallel-series memories, mostly abbreviated to SPS memories, are generally known. The data are serially supplied to the input register and are transferred to the parallel section via the parallel outputs of the input register. The output register is provided with a number of parallel inputs and a series output. Via the parallel inputs, data can be transferred simultaneously to the series output register and be read out serially at the outputs.
In memories of the kind mentioned in the opening paragraph, which are known inter alia from the chapter "Interlaced SPS" on pages 200 ff. of the book "Charge-Coupled Devices and Systems" of Howes and Morgan, published by John Wiley and Sons Ltd., Edition 1980, one stage of the series registers corresponds to to two parallel registers. During the read-in operation, the series input register is filled twice with a subline. These sublines are interlaced to a complete line in the parallel section. At the other end of the parallel section, this line is split up again into a number of sublines, which are read out successively via the series output register (de-interlacing). This interlace-de-interlace method has a number of important advantages, the main advantage residing in the fact that an increase of the packing density in the parallel section and hence a large gain in space can be obtained. For this reason, SPS memories are provided practically always with duel interlacing, the storage capacity in the parallel section thus being per line twice the capacity of the series registers. For the sake of simplicity, it will be assumed hereinafter that the factor is n=2, but it should be considered that this is not essential to the invention and that n may also be larger than 2.
A specific Application of the SPS memory is described inter alia in the article "A digital field memory for television receivers" of H.J. Pelgrom et al in I.E.E.E. Transactions on Consumer Electronics, Volume CE-29, No.3, Aug. 1983, p. 242/248. In this application, the SPS memory is used for storing video information of a T.V.frame in digitized form.
For this application as picture memory, it is desirable that a memory is available which can be used practically universally in different video systems (PAL and NTSC) both for the standard signals (625 lines-525 lines) and for non-standard signals, which may be generated, for example, for a VCR. As a result, it may happen that the number of lines in the memory in a practical application is too large. As already stated in the aforementioned publication, an excess number of lines not filled with active video data may be passed on at an increased speed during the fly-back time. In this manner, it is possible to shorten the time of residence in the memory and hence to adapt the memory to the specific application. In the normal mode, the de-interlacing electrodes are operated in such a manner that during the first half line only signals of, for example, the odd parallel channels 1,3,5 etc. are passed on from the parallel section to the series output register, while in the second half of a line period this is the case only for the signals of the even parallel channels.
The lines not filled with active video information when passed on at an increased speed will generally contain charge. Therefore, it should be ensured that also when the excess number of lines is passed on at an increased speed, the de-interlacing electrode structure is always entirely emptied.